Silicon Power SOC_IRONWOOD_FF900 PCIE Card

Design Challenges:

1. The layer structure adopts HDI structure, there is no STUB, and no back drilling design is needed;

2. The signal transmission rate is 30GB/S, it is necessary to consider signal quality and interference;

3. In order to ensure the quality of high-speed signals, the power module is placed on the left side of the board frame; there are various types of power sources on the board, and the horizontal channels are limited by the board frame; combined with the prohibition of high-speed signal through-holes, the power channels are even more limited. Reasonably plan the power layer, prioritize ensuring that the main power path meets the current carrying requirements; after ensuring that high-speed signals have sufficient spacing from other signals, fully utilize the routing layer as a power channel; consider having a complete ground plane reference for high-speed signals, other important signals should have complete references as much as possible, then cut out the middle ground plane area as a power plane to meet current carrying requirements;

4. Strictly control line spacing and length matching;

5. FPGA uses blind buried hole routing;

6. The routing of DDR, USB, Ethernet, PCIE, SATA, RS485, HDMI all use differential signal routing. In order to compensate for impedance matching, a matching resistor is added between the receiving end differential lines.

FF900 Chip Functional Structure Diagram:

FF900 BGA Pin Definitions

Some Schematics:

Bypass Capacitor

HDMI

LCD

Ethernet

Partial Layout Details Display

1: The layout of FPGA and DDR3 strictly follows the hardware development standards to avoid data transmission anomalies.

2: The MCU and SDA7123 need to consider impedance design and signal synchronization.

3: The PCB power voltage values are relatively low, with main circuit voltages such as 5V, 3.3V, 2.5V, 1.2V, 1.8V, 1.0V, etc. When the current carrying capacity is adequate, it is still advisable to maximize the plane and add more layer-changing holes, leaving some redundancy to avoid abnormal heating due to circuit design reasons; therefore, the power distribution is concentrated on the left side of the PCB.

4: To avoid signal interference between signal transmission layers, signal layer circuit routing is prohibited for high-speed signal through-holes (L2, L4, L6, L8, L11, L13, L15) six-layer lines.

PCB Simulation Diagram: